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? semiconductor components industries, llc, 2013 may, 2013 ? rev. 12 1 publication order number: noii5sm1300a/d noii5sm1300a ibis5 1.3 megapixel cmos image sensor features ? 1280 x 1024 active pixels ? 6.7 m x 6.7 m square pixels ? 2/3? optical format ? global and rolling shutter ? master clock: 40 mhz ? 27 fps (1280 x 1024) and 106 fps (640 x 480) ? on-chip 10-bit adcs ? serial peripheral interface (spi) ? windowing (roi) ? sub-sampling: 1:2 mode ? supply voltage ? analog: 3.0 v to 4.5 v ? digital: 3.3 v ? i/o: 3.3 v ? power consumption: 200 mw ? ? 30 c to +65 c operating temperature range ? 84-pin lcc package ? these devices are pb ? free and are rohs compliant applications ? machine vision ? robotics ? inspection ? traffic monitoring description the ibis5-1300 is a solid state cmos image sensor that integrates the functionality of complete analog image acquisition, digitizer, and digital signal processing system on a single chip. this 1.3-mega pixel (1280 x 1024) cmos active pixel sensor dedicated to industrial vision applications features both rolling and snapshot (or global) shutter. full frame readout time is 36 ms (max. 27.5 fps), and readout speed are boosted by windowed region of interest (roi) readout. another feature includes the double and multiples slope functionality to capture high dynamic range scenes. the sensor is available in a monochrome version or bayer (rgb) patterned color filter array. user programmable row and column start/stop positions allow windowing down to a 2x1 pixel window for digital zoom. sub sampling or viewfinder mode reduces resolution while maintaining the constant field of view and an increased frame rate. an on-chip analog signal pipeline processes the analog video output of the pixel array. double sampling (ds) eliminates the fixed pattern noise. the programmable gain and offset amplifier maps the signal swing to the adc input range. a 10-bit adc converts the analog data to a 10-bit digital word stream. the sensor uses a 3-wire serial peripheral interface (spi), or a 16-bit parallel interface. it operates with a 3.3 v power supply and requires only one master clock for operation up to 40 mhz. it is housed in an 84-pin ceramic lcc package. ordering information marketing part number description package device status noii5sm1300a-qdc mono with glass 84 ? pin lcc end ? of ? life (eol) last time buy pcn close date: october 29, 2011 noii5sm1300a-qwc mono without glass NOII5SC1300A-QDC color with glass noii5fm1300a-qdc mono on thicker epitaxial layer, with glass note: see ordering code information on page 33 for more information. http://onsemi.com figure 1. ibis5 ? 1300 photo
noii5sm1300a http://onsemi.com 2 contents features 1 ..................................... applications 1 ................................. description 1 .................................. ordering information 1 ......................... contents 2 .................................... specifications 3 ................................ key specifications 3 .......................... electrical specifications 4 ...................... architecture and operation 5 .................... floor plan 5 ................................. pixel 6 ..................................... image core operation 9 ........................ x ? addressing 11 .............................. y ? addressing 11 .............................. output amplifier 12 ............................ analog-to-digital converter 13 ................... electronic shutter types 15 ...................... sequencer 15 ................................. timing diagrams 20 ............................. frame rate 20 ................................ timing requirements 20 ........................ global shutter: single slope integration 21 ......... global shutter: pixel readout 21 .................. global shutter: multiple slope integration 23 ........ rolling shutter operation 24 ..................... windowing in x-direction 24 .................... windowing in y-direction 25 .................... initialization (startup behavior) 25 ................ package information 26 .......................... pin list 26 ................................... pad position and packaging 29 ................... package drawing with glass 30 .................. glass lid 32 .................................. handling precautions 32 ......................... limited warranty 32 ............................ return material authorization (rma) 32 ........... rohs (pb-free) compliance 32 ................... acceptance criteria specification 33 ............... ordering code definition 33 ......................
noii5sm1300a http://onsemi.com 3 specifications key specifications table 1. general specifications parameter specifications active pixels 1280 (h) x 1024 (v) pixel size 6.7 m x 6.7 m master clock 40 mhz shutter type global and rolling shutter frame rate 27 fps at full resolution windowing (roi) randomly programmable roi read out. implemented as scan- ning of lines or columns from an uploaded position adc resolution 10-bit, on-chip extended dynamic range global shutter: up to 4 slopes rolling shutter: double slope power dissipation 200 mw table 2. electro optical specifications parameter specifications sensitivity 8.4 v/lux.s at 650 nm full well charge 62500 e - temporal noise 2.5 lsb10 parasitic light sensitivity 3% dark noise 21 e - signal to noise ratio 64 db fixed pattern noise (fpn) 4.5 lsb10 dark signal 5.5 lsb10/sec at 30 c table 3. recommended operating ratings symbol description min max units t j (note 2) operating temperature range ? 30 +65 c table 4. absolute maximum ratings (note 1) symbol parameter min max units abs (3.0 v to 3.3 v supply group) abs rating for 3.0 v and 3.3 v supply group ?0.5 4.3 v abs (4.5 v supply group) abs rating for 4.5 v supply group ?0.5 (v dd + 0.5) v t s (note 1) abs storage temperature range ? 30 150 c abs storage humidity range 5 90 %rh %rh humidity (relative) - 85% at 85 c electrostatic discharge (esd) (note 3) human body model (hbm) (note 4) v charged device model (cdm) lu (note 3) latch-up (note 5) ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. absolute maximum ratings are limits beyond which damage may occur. long term exposure toward the maximum storage temperature accelerates color filter degradation. 2. operating ratings are conditions in which operation of the device is intended to be functional. 3. on semiconductor recommends that customers become familiar with, and follow the procedures in jedec standard jesd625 ? a. refer to application note an52561. 4. the ibis5 ? 1300 complies with jesd22 ? a114 hbm class 0 and jesd22 ? c101 class i. it is recommended that extreme care be taken while handling these devices to avoid damages due to esd event. refer to application note an52561. 5. the ibis5 ? 1300 does not have latch ? up protection.
noii5sm1300a http://onsemi.com 4 electrical specifications recommended operating conditions table 5. recommended operating conditions parameter description typical currents peak currents min typ max units vddh voltage on hold switches. 0.047 ma 100 ma +3.3 +4.5 +4.5 v vddr_left highest reset voltage. 0.050 ma 100 ma +3.3 +4.5 +4.5 v vddc pixel core voltage. 0.052 ma 100 ma +2.5 +3.0 +3.3 v vdda analog supply voltage of the image core. 19.265 ma n/a +3.0 +3.3 +3.6 v vddd digital supply voltage of the image core. 5.265 ma n/a +3.0 +3.3 +3.6 v idda_adc analog supply of adc 34.5 ma n/a n/a n/a n/a ma iddd_adc digital supply of adc 10.5 ma n/a n/a n/a n/a ma t a commercial operating temperature. n/a n/a ? 30 30 65 c all parameters are characterized for dc conditions after thermal equilibrium is established. always tie unused inputs to an appropriate logic level, for example, either vdd or gnd. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, take normal precautions to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit. dc electrical characteristics table 6. dc electrical characteristics parameter characteristic condition min max unit v ih input high voltage 2.1 ? v v il input low voltage ? 0.6 v i in input leakage current v in = vdd or gnd ?10 +10 a v oh output high voltage vdd = min; i oh = ?100 a 2.2 ? v v ol output low voltage vdd = min; i oh = 100 a 0.5 v i dd maximum operating current system clock 40 mhz 40 60 ma
noii5sm1300a http://onsemi.com 5 architecture and operation this section presents detailed information about the most important sensor blocks figure 2. block diagram of ibis5 ? 1300 image sensor x ? addressing ar column amplifiers nalog multiplexe pixel output amplifier pixel core g adc sequencer ima er core r y ? senso t lef y-right addressing external connection addressing system clock 40 mhz reset sample select column output c floor plan figure 2 shows the architecture of the ibis5-1300 image sensor. it consists basically of a pixel array, one x- and two y-addressing registers for the readout in x- and y -direction, column amplifiers that correct for the fixed pattern noise, an analog multiplexer, and an analog output amplifier use the left y-addressing register for readout operation. use the right y -addressing register for reset of pixel rows. in multiple slope synchronous shutter mode, the right y-addressing register resets the whole pixel core with a lowered reset voltage. in rolling curtain shutter mode, use the right y-addressing register for the reset pointer in single and double slope operation to reset one pixel row. the on-chip sequencer generates most of the signals for the image core. some basic signals (such as start/stop integration, line and frame sync signals) are generated externally. a 10-bit adc is implemented on chip but electrically isolated from the image core. you must route the analog pixel output to the analog adc input on the outside.
noii5sm1300a http://onsemi.com 6 pixel a description of the pixel architecture and the color filter array follows. architecture the pixel architecture used in the ibis5-1300 is a 4-transistor pixel as shown in figure 3. implement the pixel using the high fill factor technique. the 4t-pixel features a snapshot shutter but can also emulate the 3t-pixel by continuously closing sampling switch m2. using m2 as a global sample transistor for all pixels enables the snapshot shutter mode. due to this pixel architecture, integration during read out is not possible in synchronous shutter mode. figure 3. 4t pixel architecture reset sample mux column output c m1 m2 m3 m4 color filter array the ibis5-1300 is also processed with a bayer rgb color pattern. pixel (0,0) is a green filter and is situated on a green-blue row. green1 and green2 have a slightly dif ferent spectral response due to cross talk from neighboring pixels. green1 pixels are located on a blue-green row, green2 pixels are located on a green-red row. figure 5 shows the response of the color filter array as function of the wavelength. note that this response curve includes the optical cross talk of the pixels. figure 4. color filter arrangement of pixels r g2 b g1 (0,0) figure 5. spectral response for ibis5 ? 1300 color
noii5sm1300a http://onsemi.com 7 spectral response curve figure 6. spectral response curve qe 10% qe 20% qe 30% qe 40% 0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225 400 w a ve le nght [nm] spec res [a/w] noii5sm1300a noii5fm1300a 500 600 700 800 900 1000 figure 6 shows the spectral response characteristic for the noii5sm1300a and the noii5fm1300a. the curve is measured directly on the pixels. it includes effects of non-sensitive areas in the pixel, for example, interconnection lines. the sensor is light sensitive between 400 and 1000 nm. the peak qe x ff is 30%, approximately around 650 nm. in view of a fill factor of 40%, the qe is thus close to 75% between 500 and 700 nm. the noii5fm1300a has superior response in the nir region (700-900 nm).
noii5sm1300a http://onsemi.com 8 electro-voltaic response curve figure 7. electro ? voltaic response curve 0 0,2 0,4 0,6 0,8 1 1,2 0?10000?2000030000?4000050000?6000070000?80000 # electrons output swing [v] figure 7 shows the pixel response curve in linear response mode. this curve is the relation between the electrons detected in the pixel and the output signal. the resulting voltage-electron curve is independent of any parameters (integration time, and others). the voltage to electrons conversion gain is 17.6 v/electron. noii5fm1300a: the noii5fm1300a is processed on a thicker epitaxial silicon featuring higher sensitivity in the nir (near infra red) wavelengths (700?900 nm). the spectral response curves, highlighting the difference between ibis5-1300 using the standard process and thicker epitaxial layer process are shown in figure 6 on page 7. various machine vision applications use light sources in the nir, hence the noii5fm1300a sensor has a significant sensitivity advantage in the nir domain. a drawback of the thicker epitaxial layer is a slight performance decrease in mtf (modular transfer function or electrical pixel to pixel cross-talk) as indicated in t able 7. table 7. mtf comparison direction wavelength noii5sm1300a noii5fm1300a horizontal 600 0.58 0.37 horizontal 700 0.18 horizontal 800 0.16 horizontal 900 0.07 vertical 600 0.53 0.26 vertical 700 0.16 vertical 800 0.13 vertical 900 0.11 the resulting image sharpness is hardly affected by this decreased mtf value. both ibis5-1300 versions are fully pin compatible and have identical timing and biasing.
noii5sm1300a http://onsemi.com 9 image core operation image core operation and signalling figure 8 is a functional representation of the image core without sub-sampling and column/row swapping circuits. most of the signals involved are not available from the outside because they are generated by the x-sequencer and ss-sequencer blocks. the integration of the pixels is controlled by internal signals such as reset, sample, and hold which are generated by the on-chip ss-sequencer that is controlled with the external signals ss_start and ss_stop. reading out the pixel array starts by applying a y_start together with a y_clock signal; internally this is followed by a calibration sequence to calibrate the output amplifiers (during the row blanking time). signals necessary to do this calibration are generated by the on-chip x-sequencer. this calibration sequence takes typically 3.5 s and is necessary to remove ?fixed pattern noise? of the pixels and of the column amplifiers themselves by means of a double sampling technique. after the row blanking time, the pixels are fed to the output amplifier. the pixel rate is equal to the sys_clock frequency. image core supply considerations the image sensor has several supply voltages: vddh is the voltage that controls the sample switches. do not apply a higher voltage than this to the chip. the vddr_left voltage is the highest (nominal) reset voltage of the pixel core. the vddr_right voltage is generated from the vddr_left voltage using a circuit that is programmed with the kneepoint_lsb/msb bits in the sequencer register (see also pixel reset knee ? point for multiple slope operation (bits 8, 9, and 10) on page 17). you can disconnect the vddr_right pin from the circuit and apply an external voltage to supply the multiple slope reset voltage by setting the vddr_right_ext bit in the sequencer register. when no external voltage is applied (recommended), connect the vddr_right pin to a capacitor (recommended value = 1 f). vddc is the pixel core supply. vdda is the image core and periphery analog supply. vddd is the image core and periphery digital supply . note that the ibis5-1300 image sensor has no on-chip power rejection circuitry. as a consequence all variations on the analog supply voltages can contribute to random variations (noise) on the analog pixel signal, which is seen as random noise in the image. during the camera design, take precautions to supply the sensor with very stable supply voltages to avoid this additional noise. the pixel array (vddr_left, vddh and vddc) analog supplies are especially vulnerable to this. figure 8. image core _ y start sample hold k y ? y_cloc g y ? right addressing left addressin a bus_ pixel row y_clock x addressing pixel column _ bus b _ sys clock read-pointer _ y start reset vddh vddr_left _ vddreset vddr right output amplifier vddc _ pixel a pixel pxl out b column amplifiers
noii5sm1300a http://onsemi.com 10 global shutter supply considerations the recommended supply voltage settings listed in table 8 are used when the sensor is in global shutter mode only. table 8. global shutter recommended supply settings parameter description typ units vddh voltage on hold switches. +4.5 v vddr_left highest reset voltage. +4.5 v vddc pixel core voltage. +3.3 v vdda analog supply voltage of the image core. +3.3 v vddd digital supply voltage of the image core. +3.3 v gnda analog ground. 0 v gndd digital ground. 0 v gnd_ab anti-blooming ground. 0 v dual shutter supply considerations if you analyze the supply settings listed in table 8, you can see some fixed column non-uniformities (fpn) when operating in rolling shutter mode. if a dual shutter mode (both rolling and global shutter) is required during operation, you must apply the supply settings listed in table 9 to achieve the best possible image quality. table 9. dual shutter recommended supply settings parameter description typ units vddh voltage on hold switches. +4.5 v vddr_left highest reset voltage. +4.5 v vddc pixel core voltage. +3.0 v vdda analog supply voltage of the image core. +3.3 v vddd digital supply voltage of the image core. +3.3 v gnda analog ground. 0 v gndd digital ground. 0 v gnd_ab anti-blooming ground. 0 v image core biasing signals table 10 summarizes the biasing signals required to drive the ibis5-1300. for optimization on speed and power dissipation of all internal blocks, several biasing resistors are needed. each biasing signal determines the operation of a corresponding module in the sense that it controls the speed and power dissipation. the tolerance on the dc-level of the bias levels can vary 150 mv due to process variations. table 10. overview of bias signals signal comment related module dc-level dec_cmd connect to vdda with r = 51 k and decouple to gnda with c = 100 nf. decoder stage. 1.0 v dac_vhigh connect to vdda with r = 0 . high level of dac. 3.3 v dac_vlow connect to gnda with r = 0 . low level of dac. 0.0 v amp_cmd connect to vdda with r = 51 k and decouple to gnda with c = 100 nf. output amplifier stage. 1.2 v col_cmd connect to vdda with r = 51 k and decouple to gnda with c = 100 nf. columns amplifiers stage. 1.0 v pc_cmd connect to vdda with r = 22 k and decouple to gnda with c = 100 nf. pre-charge of column busses. 1.17 v adc_cmd connect to vdda with r = 51 k and decouple to gnda with c = 100 nf. analog stage of adc. 1.0 v adc_vhigh connect to vdda with r = 230 and decouple to gnda with c = 100 nf. high level of adc. 2.7 v adc_vlow connect to gnda with r = 410 and decouple to gnda with c = 100 nf. low level of adc. 1.2 v
noii5sm1300a http://onsemi.com 11 x ? addressing because of the high pixel rate, the x-shift register selects two columns at a time for readout, so it runs at half the system clock speed. all even columns are connected to bus a; all odd columns to bus b. in the output amplifier, bus a and bus b are combined into one stream of pixel data at system clock speed. at the end of the row blanking time, the x_sync switch is closed while all other switches are open and the decoder output is fed to the register. the decoder loads a logical one in one of the registers and a logical zero in the rest. this defines the starting point of the window in the x direction. as soon as the x_sync signal is released, the register starts shifting from the start position. when no sub-sampling is required, x_sub is inactive. the pointer in the shift-register moves one bit at a time. when sub-sampling is enabled, x_sub is activated. the shift register moves two bits at a time. taking into account that every register selects two columns, hence two pixels sub-sampling results in the pattern ?xxooxxoo? when eight pixels are considered. suppose the columns are numbered from left to right starting with 0 (zero) and sub-sampling is enabled: figure 9. column structure reg(n+1) reg(n+2) reg(n) x_sync _ a x sub bab column amplifiers b a _a bus x_s bus_b wap30 x_swap12 () col i col(i+1) dec(n+1) dec(n+2) 1/2 output amplifier sys_clock col(i+3) col (i+2) if columns 1 and 2, 5 and 6, 9 and 10 ? are swapped using the swap_12 switches, a normal sub-sampling pattern of ?xoxoxoxo? is obtained. if columns 3 and 4, 7 and 8, 11 and 12 ? are swapped using the swap_30 switches, the pattern is ?oxoxoxox?. if both the swap_12 and swap_30 switches are closed, pattern ?ooxxooxx? is obtained. figure 10. row structure reg(n) reg(n+1) reg(n+2) reg(n+3) reg(n+4) srh srh srh srh y_swap12 row(n+1) row(n+2) row(n+3) row(n+4) y_swap30 y_sync y_sub dec(n+1) dec(n+2) dec(n+3) dec(n+4) because every register addresses two columns at a time, the addressable pixels range in sub-sample mode is from zero to half the maximum number of pixels in a row (only even values). for instance: 0, 2, 4, 6, 8 ? 638. table 11. x?sub-sampling patterns x_sub x_swap12 x_swap30 sub-sample pattern 0 0 0 xxxxxxxx 1 0 0 xxooxxoo 1 1 0 xoxoxoxo 1 0 1 oxoxoxox 1 1 1 ooxxooxx y ? addressing for symmetry reasons, the sub-sampling modes in the y-direction are the same as in x-direction. table 12. y?sub-sampling patterns y_sub y_swap12 y_swap30 sub-sample pattern 0 0 0 xxxxxxxx 1 0 0 xxooxxoo 1 1 0 xoxoxoxo 1 0 1 oxoxoxox 1 1 1 ooxxooxx in normal mode, the pointer for the pixel row is shifted one at a time. when sub-sampling is enabled, y_sync is activated. the y-shift register shifts 2 succeeding bits and skips the 2 next bits. this results in pattern ?xxooxxoo?. activating y_swap12 results in pattern ?xoxoxoxo?. activating y_swap30 results in pattern ?oxoxoxox?. activating both y_swap12 and y_swap30 results in pattern ?ooxxooxx?. the addressable pixel range when y-sub sampling is enabled is: 0?1, 4?5, 8?9, 12?13, ? 1020?1021
noii5sm1300a http://onsemi.com 12 output amplifier architecture and settings the output amplifier stage is user programmable for gain and offset level. gain is controlled by 4-bit wide word; of fset by a 7-bit wide word. gain settings are on an exponential scale. offset is controlled by a 7-bit wide dac, which selects the offset voltage between two reference voltages (dac_vhigh and dac_vlow) on a linear scale. the amplifier is designed to match the specifications of the imager array output. this signal has a data rate of 40 mhz. the output impedance of the amplifier is 260 ohms. at unity gain and with a mid-range offset value, the amplifier outputs a signal in between 1.59 v (light) and 2.70 v (dark). this analog range must fit to the input range of the adc, external or internal. the output swing in unity gain is approximately 1.11 v and it is maximum 1.78 v at the highest gain settings. so, the effective signal range is between 1.17 v and 2.95 v, depending on the gain and of fset settings of the amplifier. figure 11. output structure a gain [0 3] unity gain 1 s r odd even s r + dac_vhigh dac_vlow dac_raw [6:0] dac_fine [6:0] dac_raw dac_fine pxl_out + figure 11 shows the architecture of the output amplifier. the odd and even column amplifiers sample both pixel and reset value to perform a double sampling fpn correction. you can adjust two different offsets using the on-chip dac (7 bit): dac_fine and dac_raw. dac_fine is used to tune the difference between odd and even columns; dac_raw is used to add a common (both even and odd columns) to the fpn corrected pixel value. this pixel value is fed to the first amplifier stage which has an adjustable gain, controlled by a 4-bit word (?gain [0 ? 3]?). after this, a unity feedback amplifier buffers the signal and the signal leaves the chip. this second amplifier stage determines the maximal readout speed, that is, the bandwidth and the slew rate of the output signal. the whole amplifier chain is designed for a data rate of 40 mpix/s (at 20 pf). the analog output of the sensor is not designed to drive very large loads on the pcb. therefore, it is advised that the pxl_out is connected to the adc_in right below the sensor in the top layer with a thick track. it is better not to have vias on this trace. if there is a socket being used, then it is advised that we buffer the pxl_out close to the sensor output pin and then take the signal to the adc_in. output amplifier gain control the output amplifier gain is controlled by a 4-bit word set in the amplifier register (see section amplifier register (6:0) on page 19). an overview of the gain settings is given in table 13. table 13. overview gain settings bits dc gain bits dc gain 0000 1.37 1000 6.25 0001 1.62 1001 7.89 0010 1.96 1010 9.21 0011 2.33 1011 11.00 0100 2.76 1100 11.37 0101 3.50 1101 11.84 0110 4.25 1110 12.32 0111 5.20 1111 12.42 setting of the dac reference voltage in the output amplifier, the offset is trimmed by loading registers dacraw_reg and dacfine_reg. dac_raw is used to adjust the offset of the output amplifier and dac_fine is used to tune the of fset between the even and odd columns. these registers are inputs for two dacs (see figure 12) that operate on the same resistor that is connected between pins dac_vhigh and dac_vlow. the range of the dac is defined using a resistive division with r vhigh , r dac and r vlow. figure 12. internal and external adc connections r dac_vhigh dac_vlow = 0v r dac_vlow r dac_vhigh = 3.3v dac 7.88 k external internal internal external the internal resistor r dac has a value of approximately 7.88 k . the recommend resistor values for both dac_vlow and dac_vhigh are 0 .
noii5sm1300a http://onsemi.com 13 analog-to-digital converter the ibis5-1300 has a 10-bit flash analog digital converter running nominally at 40 msamples/s. the adc is electrically separated from the image sensor. tie the input of the adc (adc_in; pin 69) externally to the output (pxl_out1; pin 28) of the output amplifier. table 14. adc specifications input range 1?3 v (note 1) quantization 10 bits nominal data rate 40 msamples/s dnl (linear conversion mode) typ. < 0.5 lsb inl (linear conversion mode) typ. < 3 lsb input capacitance < 20 pf power dissipation at 40 mhz typ. 45 ma x 3.3 v = 150 mw conversion law linear / gamma-corrected 1. the internal adc range is ty pically 100 mv lower than the external applied adc_vhigh and adc_vlow voltages due to voltage drops over parasitic internal resistors in the adc. adc timing at the rising edge of sys_clock, the next pixel is fed to the input of the output amplifier. due to internal delays of the sys_clock signal, it takes approximately 20 ns before the output amplifier outputs the analog value of the pixel, as shown in figure 13. the adc converts the pixel data on the rising edge of the adc_clock, but it takes two clock cycles before this pixel data is at the output of the adc. figure 13 shows this pipeline delay due to these delays, it is advisable that a variable phase difference is foreseen between the adc_clock and the sys_clock to tune the optimal sample moment of the adc. figure 13. adc timing setting adc reference voltages figure 14. internal and external adc connections r adc_vhigh av a dc_vlow ~ 1.8 v r adc_vlow r dc_vhigh ~ 2.7 adc external internal external the internal resistor r adc has a value of approximately 585 . this results in the following values for the external resistors: resistor value (o) r adc_vhigh 360 r adc 585 r adc_vlow 1200 note that the recommended adc resistor values yield in a conversion of the full analog output swing at unity gain (v dark_analog < adc_vhigh and v light_analog > adc_vlow). the values of the resistors depend on the value of r adc . to assure proper working of the adc, make certain the voltage difference between adc_vlow and adc_vhigh is at least 1.0 v.
noii5sm1300a http://onsemi.com 14 nonlinear and linear conversion mode??gamma? correction figure 15 shows the adc transfer characteristic. the nonlinear (exponential) adc conversion is intended for gamma-correction of the images. it increases contrast in dark areas and reduces contrast in bright areas. the non-linear transfer function is given by the following equation: vin adc_vhigh adc_vhigh adc_vlow ? () * a*x b*x 2 + a*1023 b*1023 2 + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = where a = 5; b = 0.027; x = digital output code figure 15. linear and nonlinear adc conversion characteristics sensor digital outputs the digital outputs of the sensor are not designed to drive large loads. hence, the outputs cannot be used to directly drive cables or long traces on the pcb. if it is required to drive traces more than 5 inches long, it is advisable to use a buffer for all the digital signals given out by the sensor. sensor clock inputs the adc_clock and the sys_clock of the sensor are typically 180 phase shifted from each other. however, depending on the board layout, it is possible that there may be a variation (increased phase shift of adc_clock with respect to sys_clock) in the phase shift between the clocks. so, it is recommended that the phase shift between the clocks is maintained programmable. clock jitter requirements: min low time: 11.00 ns min high time: 11.00 ns max rise time: 5 ns max fall time: 5 ns max duty cycle: 47% to 53% max period jitter: 150 ps it is important that the clock is stable, reproducible and has low jitter. sys_clock and adc_clock are the most critical clocks, both clock interact in the readout path and influence the sensor performance. black calibration due to slight variations in the chip fabrication process, the output analog voltage of the pga is not perfectly matched to the input analog range of the adc. as a result, a reduced dynamic range is compared when comparing sensors/cameras from different lots. this is especially true in the dark as it is possible that a part of the analog range gets clipped when it reaches the adc. for this reason, black calibration step is required. because this is a fixed setting, and varies very slightly with temperature, the setting can be done at the factory itself. while grabbing normal images, the settings can be loaded from an on-board memory. in the ibis5 image sensor, black calibration step also tries to match the output of the odd and even channels. the steps for black calibration are - 1. put the sensor in dark. 2. change dac_raw such that no pixel or least number of pixels (assuming there are defect pixels) have a zero adc output value. 3. change dac_fine such that the average of the odd columns is almost same as the even columns. 4. change dac_raw again such that all pixels have a non-zero output, but are as close to zero as possible. 5. repeat for different gains.
noii5sm1300a http://onsemi.com 15 electronic shutter types the ibis5-1300 has two shutter types: a rolling (curtain) shutter and a global shutter. rolling (curtain) shutter the name is due to the fact that the effect is similar to a curtain shutter of a slr film camera. although it is an electronic operation, the shutter seems to slide over the image. a rolling shutter is easy and elegant to implement in a cmos sensor. in the rolling shutter mode, there are two y-shift registers. one of them points to the row that is currently being read out. the other shift register points to the row that is currently being reset. both pointers are shifted by the same y-clock and move over the focal plane. the integration time is set by the delay between both pointers. figure 16 graphically displays the relative shift of the integration times for dif ferent lines during the rolling shutter operation. each line is read and reset in a sequential way. the integration time is the same for all lines, but is shifted in time. you can vary the integration time through the int_time register (in number of lines) this indicates that all pixels are light sensitive at another period of time, and can cause some blurring if a fast moving object is captured. figure 16. rolling shutter operation when the sensor is set to rolling shutter mode, make certain to hold the input ss_start ans ss_stop low. global shutter a global (also known as synchronous or snapshot) shutter solves the inconvenience found in the rolling shutter. light integration takes place on all pixels in parallel, although subsequent readout is sequential. figure 17 shows the integration and read out sequence for the synchronous shutter. all pixels are light sensitive at the same period of time. the whole pixel core is reset simultaneously and after the integration time all pixel values are sampled together on the storage node inside each pixel. the pixel core is read out line by line after integration. note that the integration and read out cycle is carry-out in serial; that causes that no integration is possible during read out during synchronous shutter mode, the input pins ss_start and ss_stop are used to start and stop the synchronous shutter. figure 17. global shutter operation sequencer figure 8 on page 9 shows a number of control signals that are needed to operate the sensor in a particular sub-sampling mode with a certain integration time, output amplifier gain, and so on. most of these signals are generated on-chip by the sequencer that uses only a few control signals. make certain that these control signals are generated by the external system: ? sys_clock (x-clock) defines the pixel rate ? y_start pulse indicates the start of a new frame read out ? y_clock selects a new row and starts the row blanking sequence, including the synchronization and loading of the x-register ? ss_start and ss_stop control the integration period in snapshot shutter mode. the relative position of the pulses is determined by a number of data bits that are uploaded in internal registers through the serial or parallel interface. internal registers table 15 shows a list of the internal registers with a short description. in the next section, the registers are explained in more detail. on power-on, all registers in the sensor are reset to zero. to start operating the sensor, first load all the registers using the parallel or serial-3-wire interface. the value to be loaded in each register on power-on is given in the table.
noii5sm1300a http://onsemi.com 16 table 15. internal registers register bit name description 0 (0000) 11:0 sequencer register default value <11:0>: ?000011000100? 0 shutter_type 1 = rolling shutter 0 = synchronous shutter 1 frame_cal_mode 0 = fast 1 = slow 2 line_cal_mode 0 = fast 1 = slow 3 cont_charge 1 = ?continuous? precharge enabled 4 gran_x_seq_lsb granularity of the x sequencer clock 5 gran_x_seq_msb 6 gran_ss_seq_lsb granularity of the ss sequencer clock 7 gran_ss_seq_msb 8 kneepoint_lsb sets reset voltage for multiple slope operation 9 kneepoint_msb 10 kneepoint_enable 1 = enables multiple slope operation in synchronous shutter mode 11 vddr_right_ext 1 = disables circuit that generates vddr_right voltage; this allows the applic- ation of an external voltage 1 (0001) 11:0 nrof_pixels number of pixels to count (maximum 1280/2) default value <11:0>: ?001001 111111? 2 (0010) 11:0 nrof_lines number of lines to count default value <11:0>: ?001 111111111? 3 (0011) 11:0 int_time integration time default value <11:0>: ?1 11111111111? 4 (0100) 10:0 x_reg x start position (maximum 1280/2) default value <10:0>: ?00000000000? 5 (0101) 10:0 yl_reg y-left start position default value <10:0>: ?00000000000? 6 (0110) 10:0 yr_reg y-right start position default value <10:0>: ?00000000000? 7 (0111) 7:0 image core register default value <7:0>: ?00000000? 0 test_even test even columns 1 test_odd test odd columns 2 x_subsample enable sub-sampling in x-direction 3 x_swap12 swap columns 1-2, 5-6, ? 4 x_swap30 swap columns 3-4, 7-8, ? 5 y_subsample enable sub-sampling in y-direction 6 y_swap12 swap rows 1-2, 5-6, ? 7 y_swap30 swap rows 3-4, 7-8, ? 8 (1000) 6:0 amplifier register default value <6:0>: ?1010000? 0 gain<0> output amplifier gain setting 1 gain<1> 2 gain<2> 3 gain<3> 4 unity 1 = amplifier in unity gain mode 5 dual_out 1 = activates second output
noii5sm1300a http://onsemi.com 17 table 15. internal registers 8 (1000) 6 standby 0 = amplifier in standby mode 9 (1001) 6:0 dacraw_reg amplifier dac raw offset default value <6:0>: ?1000000? 10 (1010) 6:0 dacfine_reg amplifier dac fine offset default value <6:0>: ?1000000? 11 (1011) 2:0 adc register default value <2:0>: ?011? 0 tristate_out 0 = output bus in tri-state 1 gamma 0 = gamma-correction on 2 bit_inv 1 = bit inversion on output bus 12 (1100) reserved 13 (1101) reserved 14 (1110) reserved 15 (1111) reserved detailed description of internal registers sequencer register (7:0) 1. shutter type (bit 0) the ibis5-1300 image sensor has two shutter types: 0 = synchronous shutter 1 = rolling shutter 2. output amplifier calibration (bits 1 and 2) bits frame_cal_mode and line_cal_mode define the calibration mode of the output amplifier. during every row-blanking period, a calibration is done of the output amplifier. there are two calibration modes. the fast mode (0) forces a calibration in one cycle but is not so accurate and suffers from ktc noise. the slow mode (1) only makes incremental adjustments and is noise free. approximately 200 or more slow calibrations have the same effect as one fast calibration. different calibration modes are set at the beginning of the frame (frame_cal_mode bit) and for every subsequent line that is read (line_cal_mode bit). the y_start input defines the beginning of a frame, y_clock defines the beginning of a new row. 3. continuous charge (bit 3) some applications may require the use continuous charging of the pixel columns instead of a pre-charge on every line sample operation. setting bit cont_charge to ?1? activates this function. the resistor connected to pin pc_cmd controls the current level on every pixel column. 4. internal clock granularities (bits 4, 5, 6 and 7) the system clock is divided several times on-chip. half the system clock rate clocks the x-shift-register that controls the column/pixel readout. odd and even pixel columns are switched to two separate buses. in the output amplifier, the pixel signals on the two buses are combined into one pixel stream at the same frequency as sys_clock. use the bits gran_ss_seq_msb (bit 7) and gran_ss_seq_lsb (bit 6) to program the clock that drives the ?snapshot? or synchronous shutter sequencer. this way the integration time in synchronous shutter mode is a multiple of 32, 64, 128, or 256 times the system clock period. to overcome global reset issues, use the longest ss granularity (bits 6 and 7 set to ?1?). table 16. ss sequencer clock granularities gran_ss_seq_msb/ lsb ss-sequencer clock integration time step [1] 00 32 x sys_clock 800 ns 01 64 x sys_clock 1.6 s 10 128 x sys_clock 3.2 s 11 256 x sys_clock 6.4 s 1. using a sys_clock of 40 mhz (25 ns period). the clock that drives the x-sequencer is a multiple of 4, 8, 16, or 32 times the system clock. clocking the x-sequencer at a slower rate (longer row blanking time; pixel read out speed is always equal to the system_clock) results in more signal swing for the same light conditions. table 17. x sequencer clock granularities gran_x_seq_msb/ lsb x-sequencer clock integration time step [1] 00 4 x sys_clock 100 ns 01 8 x sys_clock 200 ns 10 16 x sys_clock 400 ns 11 32 x sys_clock 800 ns 1. using a sys_clock of 40 mhz (25 ns period).
noii5sm1300a http://onsemi.com 18 5. pixel reset knee-point for multiple slope operation (bits 8, 9, and 10) in normal (single slope) mode the pixel reset is controlled from the left side of the image core using the voltage applied on pin vddr_left as pixel reset voltage. in multiple slope operation, apply one or more variable pixel reset voltages. bits knee_point_msb and knee_point_lsb select the on chip-generated pixel reset voltage. bit knee_point_enable set to 1 switches control to the right side of the image core so the pixel reset voltage (vddr_right), selected by bits knee_point_msb/lsb, is used. use bit knee_point_enable only for multiple slope operation in synchronous shutter mode. in rolling shutter mode, use only the bits knee_point_msb/lsb to select the second knee-point in dual slope operation. the actual knee-point depends on vddh, vddr_left and vddc applied to the sensor. table 18. multiple slope register settings knee_point pixel reset voltage (v)vddr_right knee-point (v) msb/lsb enable 00 0 or 1 vddr_left 0 01 1 vddr_left ? 0.76 + 0.76 10 1 vddr_left ? 1.52 + 1.52 11 1 vddr_left ? 2.28 + 2.28 6. external pixel reset voltage for multiple slope (bit 11) setting bit vddr_right_ext to ?1? disables the circuit that generates the variable pixel reset voltage and uses the voltage externally applied to pin vddr_right as the double/multiple slope reset voltage. setting bit vddr_right_ext to ?0? allows you to monitor the variable pixel reset voltage (used for multiple slope operation) on pin vddr_right. nrof_pixels register (11:0) after the internal x_sync is generated (start of the pixel readout of a particular row), the pixel_valid signal goes high. the pixel_valid signal goes low when the pixel counter reaches the value loaded in the nrof_pixel register. due to the fact that two pixels are read at the same clock cycle, you must divide this number by 2 (nrof_pixels = (width of roi / 2) ? 1). rof_lines register (11:0) after the internal yl_sync is generated (start of the frame readout with y_start), the line counter increases with each y_clock pulse until it reaches the value loaded in the nrof_lines register and generates a last_line pulse. it must be noted that the value loaded in the register must be (number of lines required - 1). int_time register (11:0) use the int_time register to set the integration time of the electronic shutter. the interpretation of the int_time depends on the chosen shutter type (rolling or synchronous). ? global shutter after the ss_start pulse is applied an internal counter counts the number of ss granulated clock cycles until it reaches the value loaded in the int_time register and generates a time_out pulse. use this time_out pulse to generate the ss_stop pulse to stop the integration. when the int_time register is used, the maximum integration time is: tint_max = [4095 * 256 (max granularity) * (40 mhz) ?1] = 26.2 ms. you can increase this maximum time if you use an external counter to trigger ss_stop. ten is the minimal value that you can load into the int_time register (see also internal clock granularities (bits 4, 5, 6 and 7) on page 17). ? rolling shutter when the y_start pulse is applied (start of the frame readout), the sequencer generates the yl_sync pulse for the left y -shift register (read out y-shift register). this loads the left y-shift register with the pointer loaded in yl_reg register. at each y_clock pulse, the pointer shifts to the next row and the integration time counter increases until it reaches the value loaded in the int_time register. at that moment, the sequencer generates the yr_sync pulse for the right y-shift register; it loads the right y-shift register (reset y-shift register) with the pointer loaded in yr_reg register (see figure 18). the integration time counter is reset when the sync for the left y-shift register, yl_sync is asserted. both shift registers keep moving until the next sync is asserted, i.e., the yl_sync for the left y-shift register (generated by y_start) and the yr_sync for the right y-shift register (generated when the integration time counter reaches the int_time value). treg_int difference between the left and right pointer = value set in the int_time register (number of lines). the actual integration time is given by tint integration time [# lines] = nrof_lines register ? int_time register. tint integration time [# lines] = nrof_lines register ? int_time register.
noii5sm1300a http://onsemi.com 19 figure 18. synchronization of shift registers in rolling shutter mode line n t reg_int last line, followed by sync of left shift-register t int sync sync of right shift-register sync of left shift-register x_reg register (10:0) the x_reg register determines the start position of the window in the x-direction. in this direction, there are 640 possible starting positions (two pixels are addressed at the same time in one clock cycle). if sub sampling is enabled, only the even pixels are set as starting position (for instance: 0, 2, 4, 6, 8 ? 638). yl_reg (10:0) and yr_reg (10:0) the yl_reg and yr_reg registers determine the start position of the window in the y-direction. in this direction, there are 1024 possible starting positions. in rolling shutter mode the yl_reg register sets the start position of the read (left) pointer and the yr_reg sets the start position of the reset (right) pointer. for both shutter types yl_reg is always equal to yr_reg. image core register (7:0) bits 1:0 of the image_core register define the test mode of the image core. setting 00 is the default and normal operation mode. in case the bit is set to ?1?, the odd (bit 1) or even (bit 0) columns are tight to the reset level. if the internal adc is used, bits 0 and 1 are used to create test pattern to test the sample moment of the adc. if the adc sample moment is not chosen correctly, the created test pattern is not black-white-black-etc. (image_core register set at 1 or 2) or black-black-white-white-black-black (image_core register set at 9) but grey shadings if the sensor is saturated. bits 7:2 of the image_core register define the sub-sampling mode in the x-direction (bits 4:2) and in the y-direction (bits 7:5). the sub-sampling modes and corresponding bit setting are given in table 11 and table 12 on page 11. amplifier register (6:0) 1. gain (bits 3:0) the gain bits determine the gain setting of the output amplifier. they are only effective if unity = 0. the gains and corresponding bit setting are given in table 13 on page 12. 2. unity (bit 4) in case unity = 1, the gain setting of gain is bypassed and the gain amplifier is put in unity feedback. 3. dual_out (bit 5) if dual_out = 1, the two output amplifiers are active. if dual_out = 0, the signals from the two buses are multiplexed to output pxl_out1 which connects to adc_in. the gain amplifier and output driver of the second path are put in standby. 4. standby if standby = 0, the complete output amplifier is put in standby. for normal use, set standby to ?1?. dac_raw register (6:0) and dac_fine (6:0) register these registers determine the black reference level at the output of the output amplifier. bit setting 1 111111 for the dac_raw register gives the highest offset voltage. bit setting 0000000 for the dac_raw register gives the lowest offset voltage. ideally, if the two output paths have no of fset mismatch, the dac_fine register is set to 1000000. deviation from this value is used to compensate the internal mismatch (see output amplifier on page 12). adc register (2:0) 1. tristate_out (bit 0) in case tristate = 0, the adc_d<9:0> outputs are in tri-state mode. tristate = 1 for normal operation mode. 2. gamma (bit 1) if gamma is set to ?1?, the adc input to output conversion is linear; otherwise the conversion follows a ?gamma? law (more contrast in dark parts of the window, lower contrast in the bright parts). 3. bit_inv (bit 2) if bit_inv = 1, 0000000000 is the conversion of the lowest possible input voltage, otherwise the bits are inverted. data interfaces two different data interfaces are implemented. they are selected using pins if_mode (pin 12) and ser_mode (pin 6). table 19. serial and parallel interface selection if_mode ser_mode selected interface 1 x parallel 0 1 serial 3 wire parallel interface the parallel interface uses a 16-bit parallel input (p_data (15:0)) to upload new register values. asserting
noii5sm1300a http://onsemi.com 20 p_write loads the parallel data into the internal register of the ibis5-1300 where it is decoded (see figure 19). p_data (15:12) address bits reg_addr (3:0); p_data (11:0) data bits reg_data (11:0). serial 3-wire interface the serial 3-wire interface (or serial-to-parallel interface) uses a serial input to shift the data in the register buffer. when the complete data word is shifted into the register buffer the data word is loaded into the internal register where it is decoded (see figure 19). s_data (15:12) address bits reg_addr (3:0); s_data (11:0) data bits reg_data (11:0). when s_en is asserted the parallel data is loaded into the internal registers of the sensor. the maximum tested frequency of s_data is 2.5 mhz.) the serial 2-wire interface is not operational in the ibis5-1300 image sensor. use the 3-wire spi interface to load the sensor registers. figure 19. parallel interface timing timing diagrams frame rate the pixel rate for this sensor is high enough to support a frame rate of greater than 100 hz for a window size of 640 x 480 pixels (vga format). considering a row blanking time of 3.5 s (as baseline, see also internal clock granularities (bits 4, 5, 6 and 7) on page 17), this requires a minimum pixel rate of nearly 40 mhz. the final bandwidth of the column amplifiers, output stage, and others is determined by external bias resistors. with a nominal pixel rate of 40 mhz, a full frame rate of a little more than 27 frames per second is obtained. the frame period of the ibis5-1300 sensor depends on the shutter type. rolling shutter => frame period = (nr. lines * (rbt + pixel period * nr. pixels)) with: nr. lines number of lines read out each frame (y) nr. pixels number of pixels read out each line (x) rbt row blanking time = 3.5 s (typical) pixel period 1/40 mhz = 25 ns example read out time of the full resolution at nominal speed (40 mhz pixel rate): frame period = (1024 * (3.5 s + 25 ns * 1280)) = 36.4 ms = 27.5 fps global shutter frame period = tint + tread out = tint + (nr. lines * (rbt + pixel period * nr. pixels)) with: tint integration (exposure) time nr. lines number of lines read out each frame (y) nr. pixels number of pixels read out each line (x) rbt row blanking time = 3.5 s (typical) pixel period 1/40 mhz = 25 ns example read out time of the full resolution at nominal speed (40 mhz pixel rate) with an integration time of 1 ms: frame period = 1 ms + (1024 * (3.5 s + 25 ns * 1280)) = 37.4 ms = 26.8 fps region-of-interest (roi) read out windowing is easily achieved by uploading the starting point of the x- and y-shift registers in the sensor registers using the various interfaces. this downloaded starting point initiates the shift register in t he x- and y-direction triggered by the y_start (initiates the y-shift register) and the y_clk (initiates the x-shift register) pulse. the minimum step size for the x-address is two (only even start addresses are chosen) and one for the y-address (every line is addressable). the frame rate increases almost linearly when fewer pixels are read out. table 20 gives an overview of the achievable frame rates (in rolling shutter mode) with various roi dimensions. table 20. frame rate vs. resolution image resolution (x x y) frame rate [frames/s] frame readout time [ms] comment 1280 x 1024 27 36 full resolution. 640 x 480 100 10 roi read out. 100 x 100 1657 0.6 roi read out. timing requirements there are six control signals that operate the image sensor: ? ss_start ? ss_stop ? y_clock ? y_start ? x_load ? sys_clock the external system generates these control signals with following time constraints to sys_clock (rising edge = active edge): t setup >7.5 ns t hold > 7.5 ns it is important that these signals are free of any glitches.
noii5sm1300a http://onsemi.com 21 figure 20 shows a recommended schematic for generating the basic signals and to avoid any timing problems. figure 20. recommended schematic for basic signals ff sys_clock_n sys_clock ss_start ss_stop y_clock y_start x_load figure 21. relative timing of 5 ? sequencer control signal global shutter: single slope integration ss_start and ss_stop must change on the falling edge of the sys_clock (tsetup and thold > 7.5 ns). make certain that the pulse width of both signals is a minimum of 1 sys_clock cycle. as long as ss_start or ss_stop are asserted, the sequencer stays in a suspended state (see figure 22). t 1 - time counted by the integration timer until the value of int_time register is reached. the integration timer is clocked by the granulated ss-sequencer clock. t 2 - time_out signal stays high for one granulated ss-sequencer clock period. t 3 - there are no constraints for this time. use the time_out signal to trigger the ss_stop pin (or use an external counter to trigger ss_stop); you cannot tie both signals together. t 4 - during this time, the ss-sequencer applies the control signals to reset the image core and start integration. this takes four granulated ss-sequencer clock periods. the integration time counter starts counting at the first rising edge after the falling edge of ss_start. t 5 - the ss-sequencer puts the image core in a readable state. it takes two granulated ss-sequencer clock periods. t int - the ?real? integration or exposure time. figure 22. global shutter: single slope integration global shutter: pixel readout basic operation y_start and y_clock must change on the falling edge of the sys_clock (tsetup and thold > 7.5 ns). make certain that the pulse width is a minimum of one clock cycle for y_clock and three clock cycles for y_start. as long as y_clock is applied, the sequencer stays in a suspended state. (see figure 23) t 1 - row blanking time: during this period, the x-sequencer generates the control signals to sample the pixel signal and pixel reset levels (double sampling fpn-correction), and starts the readout of one line. the row blanking time depends on the granularity of the x-sequencer clock (see table 21 on page 22).
noii5sm1300a http://onsemi.com 22 t 2 - pixels counted by pixel counter until the value of nrof_pixels register is reached. pixel_valid goes high when the internal x_sync signal is generated, in other words when the readout of the pixels is started. pixel_valid goes low when the pixel counter reaches the value loaded in the nrof_pixels register (after a complete row read out). t 3 - last_line goes high when the line counter reaches the value loaded in the nrof_lines register and stays high for one line period (until the next falling edge of y-clock). on y_start the left y -shift-register of the image core is loaded with the yl-pointer that is loaded in to register yl_reg. advanced operation: it was observed during characterization of the ibis5-1300 image sensor that there are column non-uniformities in the image in synchronous shutter mode, when the y-readout pointer is still selecting a line during the global reset for the next frame. to avoid this problem, an advanced timing has been generated for the synchronous shutter mode. see question 12 in an6004, frequently asked questions about the ibis5 device for more information. the application note discusses the cause and corrective action for this problem. figure 23. global shutter: pixel read out pixel output the pixel signal at the pxl_out1 output becomes valid after five sys_clock cycles when the internal x_sync (start of pixel_valid output or external x_load pulse) pulse is asserted (see figure 24). t 1 - row blanking time (see table 21). t 2 - 5 sys_clock cycles. t 3 - time for new x-pointer position upload in x_reg register (see w indowing in x ? direction on page 24 for more details). table 21. row blanking time as function of x ? sequencer granularity granularity n gran t 1 ( s) = 35 x n gran x t sys_clock gran_x_seq msb/lsb x 4 140 x t sys_clock = 3.5 00 x 8 280 x t sys_clock = 7.0 01 x 16 560 x t sys_clock = 14.0 10 x 32 1120 x t sys_clock = 28.0 11 figure 24. pixel output
noii5sm1300a http://onsemi.com 23 global shutter: multiple slope integration figure 25. multiple slope integration use up to four different pixel reset voltages during multiple slope operation in synchronous shutter mode. this is done by uploading new values to register bits kneepoint_msb/lsb/enable before a new ss_start pulse is applied. set bit kneepoint_enable high to do a pixel reset with a lower voltage. set bits kneepoint_msb/lsb/enable back to ?0? before the ss_stop pulse is applied. every time an ss_start pulse is applied, the integration time counter is reset. the time_out signal cannot be used in multi-slope operation to determine the location of the next ss_start or ss_stop pulse. external counters must be used for generating these signals. table 22. multiple slope register settings kneepoint msb/lsb enable initial setup 00 0 1st register upload 01 1 2nd register upload 10 1 3th register upload 11 1 4th register upload 00 0 upload the register after time t stable , otherwise, the change affects the ss-sequencer resulting in a bad pixel reset. t stable depends on the granularity of the ss-sequencer clock (see table 23). table 23. t stable for different granularity settings granularity n gran t stable ( s) = 5 x n gran x t sys_clock gran_ss_seq msb/lsb x 32 160 x t sys_clock = 4 00 x 64 320 x t sys_clock = 8 01 x 128 640 x t sys_clock = 16 10 x 256 1280 x t sys_clock = 32 11 t upload depends on the interface mode used to upload the registers. table 24. t upload for different interface modes interface mode t upload ( s) parallel 1 serial 3-wire 8
noii5sm1300a http://onsemi.com 24 rolling shutter operation the integration of the light in the image sensor is done during readout of the other lines. the only difference with synchronous shutter is that the time_out pin is used to indicate when the y_sync pulse for the right y-shift-register (reset y-shift register) is generated. this loads the right y-shift-register with the pointer loaded in register yr_reg. the y_sync pulse for the left y-shift register (read y-shift register) is generated with y_start. the int_time register defines how many lines to count before the y_sync of the right y-shift-register is generated, hence defining the integration time. see also int_time register (11:0) on page 18 for a detailed description of the rolling shutter operation. t int integration time [# lines] = register(nrof_lines) ? register(int_time) note: for normal operation the values of the yl_reg and yr_reg registers are equal. windowing in x-direction an x_load pulse overrides the internal x_sync signal, loading a new x-pointer (stored in the x_reg register) into the x-shift-register. the x_load pulse must appear on the falling edge of sys_clock and remain high for two sys_clock cycles overlapping two rising edges of sys_clock. the new x-pointer is loaded on one of the two rising edges of sys_clock. the available time to upload the register is t load ; it is defined from the previous register load to the rising edge of x_load. it depends on the settling time of the register and the x-decoder. table 25. t load for different interfaces interface mode t load ( s) parallel interface 1 (about 40 sys_clock cycles) serial 3 wire 16 (at 2.5 mhz data rate) the actual time to load the register itself depends on the interface mode that is used. the parallel interface is the fastest. figure 26. rolling shutter operation figure 27. windowing in x ? direction
noii5sm1300a http://onsemi.com 25 windowing in y-direction reapply the y_start pulse after loading a new y-pointer value into the yl_reg and yr_reg registers to load a new y-pointer into the y-shift-register. every time a y_start pulse appears, a frame calibration of the output amplifier occurs. initialization (startup behavior) to avoid any high current consumption at startup, apply the sys_clock signal as soon as possible after or even before power on of the image sensor. after power on, apply sys_reset for a minimum of five sys_clock periods to ensure a proper reset of the on-chip sequencer and timing circuitry. all internal registers are set to ?0? after sys_reset is applied. because all the ibis5-1300 control signals are active high, apply a low level (before sys_reset occurs) to these pins at start up to avoid latch up. figure 28. windowing in y ? direction
noii5sm1300a http://onsemi.com 26 package information pin list the ibis5-1300 image sensor has 84 pins and is packaged in a leadless ceramic carrier (lcc) package. table 26 lists the pins and their functions. table 26. pin list (notes 1, 2 and 3) pin pin name pin type pin description 1 p_data<8> input digital input. data parallel interface. 2 p_wr input digital input (active high). parallel write. 3 s_clk input digital input. clock signal of serial interface. 4 s_data input digital input/output. data of serial interface. 5 s_en input digital input (active low). enable of serial 3-wire interface. 6 ser_mode input digital input. serial mode enable (1 = enable serial 3-wire). 7 vddc supply analog supply voltage. supply voltage of the pixel core [3.3 v]. 8 vdda supply analog supply voltage. analog supply voltage of the image sensor [3.3 v]. 9 gnda ground analog ground. analog ground of the image sensor. 10 gndd ground digital ground. digital ground of the image sensor. 11 vddd supply digital supply voltage. digital supply voltage of the image sensor [3.3 v]. 12 if_mode input digital input. interface mode (1 = parallel; 0 = serial). 13 dec_cmd input analog input. biasing of decoder stage. connect to vdda with r = 50 k and decouple with c = 100 nf to gnda. 14 y_start input digital input (active high). start frame read out. 15 y_clock input digital input (active high). line clock. 16 last_line output digital output. generates a high level when the last line is read out. 17 x_load input digital input (active high). loads new x-position during read out. 18 sys_clock input digital input. system (pixel) clock (40 mhz). 19 pxl_valid output digital output. generates high level during pixel read out. 20 ss_start input digital input (active high). start synchronous shutter operation. 21 ss_stop input digital input (active high). stop synchronous shutter operation. 22 time_out output digital output. global shutter: pulse when timeout reached. it is used to trigger ss_stop; do not tie both signals together. rolling shutter: pulse when second y-sync appears. 23 sys_reset input digital input (active high). global system reset. 24 el_black input digital input (active high). enables electrical black in output amplifier. 25 eosx output digital output. diagnostic end-of-scan of x-register. 26 dac_vhigh input analog reference input. biasing of dac for output dark level. use this to set the output range of dac. default: connect to vdda with r = 0 . 27 dac_vlow input analog reference input. biasing of dac for output dark level. use this to set the output range of dac. default: connect to gnd a with r = 0 . 28 pxl_out1 output analog output. analog pixel output 1. 29 pxl_out2 output analog output. analog pixel output 2. leave not connected if not used. 30 amp_cmd input analog input. biasing of the output amplifier. connect to vdda with r = 50 k and decouple with c = 100 nf to gnda. 1. all pins with the same name can be connected together. 2. all digital input are active high (unless mentioned otherwise). 3. tie all digital inputs that are not used to gnd (inactive level).
noii5sm1300a http://onsemi.com 27 table 26. pin list (notes 1, 2 and 3) pin pin description pin type pin name 31 col_cmd input analog input. biasing of the column amplifiers. connect to vdda with r = 50 k and decouple with c = 100 nf to gnda. 32 pc_cmd input analog input. pre-charge bias. connect to vdda with r = 25 k and decouple with c = 100 nf to gnda. 33 vddd supply digital supply. digital supply voltage of the image sensor [3.3 v]. 34 gndd ground digital ground. digital ground of the image sensor. 35 gnda ground analog ground. analog ground of the image sensor. 36 vdda supply analog supply voltage. analog supply voltage of the image sensor [3.3 v]. 37 vddc supply analog supply voltage. supply voltage of the pixel core [3.3 v]. 38 p_data<0> input digital input. data parallel interface (lsb). 39 p_data<1> input digital input. data parallel interface. 40 p_data<2> input digital input. data parallel interface. 41 p_data<3> input digital input. data parallel interface. 42 p_data<4> input digital input. data parallel interface. 43 p_data<5> input digital input. data parallel interface. 44 p_data<6> input digital input. data parallel interface. 45 p_data<7> input digital input. data parallel interface. 46 si2_addr<0> input digital input. connect to gndd. 47 si2_addr<1> input digital input. connect to gndd. 48 si2_addr<2> input digital input. connect to gndd. 49 si2_addr<3> input digital input. connect to gndd. 50 si2_addr<4> input digital input. connect to gndd. 51 gndab supply analog supply voltage. anti-blooming ground. 52 vddr_right supply analog supply voltage. variable reset voltage (multiple slope operation). decouple with 1 f to gnda. 53 adc_vlow input analog reference input. adc low reference voltage. default: connect to gnda with r = 1200 and decouple with c = 100 nf to gnda. 54 adc_gnda ground analog ground. adc analog ground. 55 adc_vdda supply analog supply voltage. adc analog supply voltage [3.3 v]. 56 adc_gndd ground digital ground. adc digital ground. 57 adc_vddd supply digital supply voltage. adc digital supply voltage [3.3 v]. 58 adc_clock input digital input. adc clock (40 mhz). 59 adc_out<9> output digital output. adc data output (msb). 60 adc_out<8> output digital output. adc data output. 61 adc_out<7> output digital output. adc data output. 62 adc_out<6> output digital output. adc data output. 63 adc_out<5> output digital output. adc data output. 64 adc_out<4> output digital output. adc data output. 65 adc_out<3> output digital output. adc data output. 66 adc_out<2> output digital output. adc data output. 67 adc_out<1> output digital output. adc data output. 1. all pins with the same name can be connected together. 2. all digital input are active high (unless mentioned otherwise). 3. tie all digital inputs that are not used to gnd (inactive level).
noii5sm1300a http://onsemi.com 28 table 26. pin list (notes 1, 2 and 3) pin pin description pin type pin name 68 adc_out<0> output digital output. adc data output (lsb). 69 adc_in input analog input. adc analog input. 70 adc_cmd input analog input. biasing of the input stage of the adc. connect to adc_vdda with r = 50 k and decouple with c = 100 nf to adc_gnda. 71 adc_vddd supply digital supply voltage. adc digital supply voltage [3.3 v]. 72 adc_gnda ground analog ground. adc analog ground. 73 adc_gndd ground digital ground. adc digital ground. 74 adc_vdda supply analog supply voltage. adc analog supply voltage [3.3 v]. 75 adc_vhigh input analog reference input. adc high reference volt age.default: connect to vdda with r = 360 and decouple with c = 100 nf to gnda. 76 vddr_left supply analog supply voltage. high reset level [4.5 v]. 77 vddh supply analog supply voltage. high supply voltage for hold switches in the image core [4.5 v] 78 p_data<15> input digital input. data parallel interface (msb). 79 p_data<14> input digital input. data parallel interface. 80 p_data<13> input digital input. data parallel interface. 81 p_data<12> input digital input. data parallel interface. 82 p_data<11> input digital input. data parallel interface. 83 p_data<10> input digital input. data parallel interface. 84 p_data<9> input digital input. data parallel interface. 1. all pins with the same name can be connected together. 2. all digital input are active high (unless mentioned otherwise). 3. tie all digital inputs that are not used to gnd (inactive level).
noii5sm1300a http://onsemi.com 29 pad position and packaging bare die the ibis5-1300 image sensor has 84 pins, 21 pins on every edge. the die size from pad-edge to pad-edge (without scribe-line) is: 10156.5 m (x) by 9297.25 m (y). scribe lines take about 100 to 150 m extra on each side. pin 1 is located in the middle of the left side, indicated by a ?1? on the layout. a logo and some identification tags are on the top right of the die. identification test structure figure 29. ibis5 ? 1300 bare die dimensions (all dimensions in m)
noii5sm1300a http://onsemi.com 30 package drawing with glass lcc84, 15.24x15.24 case 115as ? 01 issue o xxxxx = specific device code a = assembly location wl = wafer lot yy = year ww = work week generic marking diagram
noii5sm1300a http://onsemi.com 31 table 27. mechanical specifications (see package drawing with glass on page 30) parameters description min typ max units die (with pin 1 to the left center, top view) pixel (0,0) is bottom left die thickness na 0.740 na mm die center, x offset to the center of package ?50 0 50 m die center, y offset to the center of the package ?50 0 50 m die position, x tilt to the die attach plane n/a 1 n/a deg die position, y tilt to the die attach plane n/a 1 n/a deg die placement accuracy (referenced to die scribe and lead fingers on package on all four sides) ?50 0 50 m die rotation accuracy ?1 ? 1 deg distance from pcb plane to top of the die surface ? 1.26 ? mm distance from top of the die surface to top of the glass lid ? 1.69 ? mm glass lid specifications xy size ? 15 x 15 ? mm thickness 0.5 0.55 0.6 mm spectral range for optical coating of window 400 ? 1000 nm reflection coefficient for window (refer to figure 31) ? <0.8 % mechanical shock jesd22-b104c; condition g ? ? 2000 g vibration jesd22-b103b; condition 1 20 ? 2000 hz mounting profile reflow profile according to j-std-020d.1 ? ? 260 c figure 30. side view dimensions
noii5sm1300a http://onsemi.com 32 glass lid the ibis5-1300 image sensor uses a glass lid without any coatings. figure 31 shows the transmission characteristics of the glass lid. as seen in figure 31, the sensor does not use infrared attenuating color filter glass. provide a filter in the optical path when using color devices. figure 31. transmission characteristics of glass lid handling precautions for proper handling and storage conditions, refer to the on semiconductor application note an52561. information on pb-free soldering ibis5-1300 product was tested successfully for pb-free soldering processes, using a reflow temperature profile with maximum 260 c, minimum 40 s at 255 c and minimum 90 s at 217 c. limited warranty on semiconductor image sensor business unit warrants that the image sensor products to be delivered hereunder, if properly used and serviced, will conform to seller?s published specifications and will be free from defects in material and workmanship for two (2) years following the date of shipment. if a defect were to manifest itself within two (2) year period from the sale date, on semiconductor will either replace the product or give credit for the product. return material authorization (rma) on semiconductor packages all of its image sensor products in a clean room environment under strict handling procedures and ships all image sensor products in esd-safe, clean-room-approved shipping containers. products returned to on semiconductor for failure analysis should be handled under these same conditions and packed in its original packing materials, or the customer may be liable for the product. rohs (pb-free) compliance this paragraph reports the use of hazardous chemical substances as required by the rohs directive (excluding packing material). lead, cadmium, mercury hexavalent chromium, pbb (polybrominated biphenyls), pbde (polybrominated diphenyl ethers), noted as ?intentional content?: is not available in the ibis5-1300. note: ?intentional content? is defined as any material demanding special attention that is allowed into the product as follows: ? a chemical composition is added into the inquired product intentionally to produce and maintain the required performance and function of the product. ? a chemical composition which is used intentionally in the manufacturing process, that is allowed into the product. the following case is not treated as ?intentional content?: ? the above material is contained as an impurity into raw materials or parts of the intended product. the impurity is defined as a substance that cannot be removed industrially, or it is produced using a process such as chemical composing or reaction, and it cannot be removed technically.
noii5sm1300a http://onsemi.com 33 acceptance criteria specification the product acceptance criteria is available on request. this document contains the criteria to which the ibis5-1300 is tested before being shipped. ordering code definition o = opto n = on semiconductor ibis5 m=mono, c=color q= lcc package commercial temperature range 1300 mq s = standard process f= thicker epitaxial 1.3 mp resolution additional functionality d= 263 glass, w=windowless i i = im age sensors no i5s a ? dc on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 noii5sm1300a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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